1. Field of the Invention
The present invention relates to a semiconductor device and a method of its fabrication, and more particularly, to a semiconductor device having a recessed landing pad and a method of its fabrication.
2. Description of the Related Art
As the integration density and operation speed of memory devices such as a Dynamic Random Access Memory (DRAM) continue to increase, it becomes necessary to reduce contact resistance and resistance of a bit line. Conventionally, a metal material like tungsten is used for the bit line. However, the bit line is connected to a lower conductive pattern such as a landing pad via a contact plug, and polysilicon is widely used for a film forming material of the landing pad. To reduce the contact resistance, a technique of forming metal silicide between the contact plug and the landing pad has been researched.
FIGS. 1 to 3 are process cross-sectional views illustrating a conventional method of fabricating a semiconductor device having a bit line and a metal silicide layer.
Referring to FIG. 1, an isolation layer 13 is formed in a semiconductor substrate 11 to define an active region 12. A lower interlayer dielectric layer 15 is formed on the entire surface of the semiconductor substrate 11 having the isolation layer 13. First and second landing pads 16 and 17 are formed through the lower interlayer dielectric layer 15 to be in contact with the active region 12. The landing pads 16 and 17 are formed of a polysilicon layer. Top surfaces of the lower interlayer dielectric layer 15 and the landing pads 16 and 17 are exposed on substantially the same plane.
An intermediate interlayer dielectric layer 25 is formed on the entire surface of the semiconductor substrate 11 having the landing pads 16 and 17. A bit line contact hole is formed through the intermediate interlayer dielectric layer 25 to expose the second landing pad 17. A plug spacer 21 is formed on sidewalls of the bit line contact hole. Subsequently, a silicidation process is carried out to form a metal silicide layer 18 in the second landing pad 17 exposed on a bottom surface of the bit line contact hole. As a result, the second landing pad 17 and the metal silicide layer 18 are sequentially stacked to constitute a bit line pad 19. In this case, a top surface of the metal silicide layer 18 is disposed on substantially the same plane as the top surface of the lower interlayer dielectric layer 15 and the top surface of the first landing pad 16.
Subsequently, a metal layer is formed, which fills the bit line contact hole and covers the intermediate interlayer dielectric layer 25. The metal layer may be formed of a tungsten layer and patterned to form a bit line 29. As a result, bit line plugs 23 are formed in the bit line contact hole. The bit line 29 is electrically connected to the bit line pad 19 via the bit line plug 23. A bit line spacer 27 is formed on sidewalls of the bit line 29. An upper interlayer dielectric layer 35 is formed on the entire surface of the semiconductor substrate 11 having the bit line 29.
Referring to FIG. 2, the upper interlayer dielectric layer 35 and the intermediate interlayer dielectric layer 25 are sequentially patterned to form a storage node contact hole 37, which exposes the first landing pad 16. An isotropic etching process is then carried out to expand the storage node contact hole 37.
While the storage node contact hole 37 is expanded, the lower interlayer dielectric layer is partially etched to be recessed downward. In addition, the metal silicide layer 18 is partially exposed. In general, the metal silicide layer 18 has a high etching rate with respect to the isotropic etching process. In this case, the metal silicide layer 18 is also partially etched by the isotropic etching process to form an air gap 18H. Consequently, a contact area between the bit line plugs 23 and the metal silicide layer 18 is significantly reduced by the air gap 18H.
Referring to FIG. 3 an insulating spacer 39 is formed on sidewalls of the expanded storage node contact hole 37. The insulating spacer 39 is formed of an insulating layer such as a silicon nitride layer. While the insulating spacer 39 is formed, the insulating layer also penetrates into the air gap 18H to form a contact barrier layer 18S.
A storage node plug 41 is then formed to fill the expanded storage node contact hole 37. A storage node 43 is formed on the storage node plug 41.
According to the conventional method of fabricating the semiconductor device as described above, a contact resistance between the bit line plugs 23 and the metal silicide layer 18 increases due to the contact barrier layer 18S. In addition it is difficult to control the contact resistance between the bit line plugs 23 and the metal silicide layer 18.
Other methods of forming a contact plug are disclosed in U.S. Pat. No. 6,136,643 entitled “Method For Fabricating Capacitor-Over-Bit-Line Dynamic Random Access Memory Using Self-Aligned Contact Etching Technology” to Jeng, et al., and are disclosed in U.S. Pat. No. 6,593,217 entitled “Method Of Manufacturing Semiconductor Device” to Fujisawa.
But even so, improved techniques of controlling a contact resistance between a bit line and a lower conductive pattern are still needed.